1. Field of the Invention
This invention relates to programmable logic devices, and in particular, to the interconnects or routing pools for such devices.
2. Description of Related Art
Integrated circuits (ICs) can be designed to implement and carry out desired functions for various applications and needs. One such IC is the application specific integrated circuit or ASIC, which are designed to carry out specific applications. However, ASICs can only be used for the applications they were desired for. As circuitry and functions become more and more complex, requiring very specific functions for the IC to perform, designing, testing, and manufacturing ASICs for very narrow uses can increase the cost per ASIC and make the ASIC cost prohibitive.
Programmable logic devices (PLDs) can implement a variety of functions using a single semiconductor chip. FIG. 1 shows a generalized PLD 100 which includes an interconnect or generic routing pool (GRP) 110, a programmable array logic (PAL) 120, and a generic logic blocks (GLBs) 130. GRP 110 is a global interconnect circuit or matrix for selecting desired signals to be applied to PAL 120, i.e., for connecting desired terms to
120. The signals can be selected from external input/output (I/O) pins, output terminals of GLBs 130, or other suitable signal sources. The total number of signals or terms input to GRP 110 can be hundreds or even thousands. The desired signals are then selected by GRP 110 and routed to input terminals of PAL 120, which is a programmable array of AND gates. After performing desired AND functions on the selected terms, the resulting product terms are input to GLBs 130. GLBs 130, also known as macrocells, contain a programmable array of OR gates for performing OR functions on the input product terms, i.e., selective summing of the product terms. In addition to OR gates, a GLB can also include other logic gates, such as exclusive OR (XOR) gates, registers, I/O cells, etc. The output signals from GLBs 130 can then be used for the desired application or can be fed back into GRP 110 for further processing.
The programmable arrays or matrices within GRP 110, PAL 120, and/or GLBs 130 are programmed according to the specification provided by the circuit designer for implementing the desired function. Programming typically involves either selectively breaking or maintaining electrical connections between GRP input signals, the AND gates, and the OR gates. FIG. 2 shows an interconnection matrix 200, which is a portion of GRP 110 for selectively making the desired connections from the input terminals to the output terminals of GRP 110. Matrix 110 has four input terminals 201-204 coupled to four corresponding columns of signal lines and three output terminals 211-213 coupled to three corresponding rows of signal lines. Note that the use of "rows" and "columns" is arbitrary, simply designating directions of the signal lines. Also, it should be noted that any number of input terminals and output terminals are possible, with the number of output terminals typically more than or equal to the number of input terminals.
The rows and columns are approximately orthogonal to each other, with a pass transistor coupled at the intersection of each row and column signal line. Each pass transistor 221-232 acts as a switch to either connect or disconnect the signal at an input terminal to the corresponding output terminal. Pass transistors 221-232 are shown as N-type transistors, although other types are also suitable. The drain of each pass transistor is coupled to a corresponding column signal line and the source of each pass transistor is coupled to a corresponding row signal line. The control gate of each pass transistor 221-232 is coupled to the output terminal of an associated programmable cell 221A-232A. Programmable cells 221A-232A, which typically include non-volatile memory cell(s), apply different voltage levels to the control gates of the pass transistors, based on user-supplied input signals to the programmable cells. In general, the programmable cells can be any circuit or device capable of holding and outputting a state and its complement in response to external inputs.
Connections from signals on the input terminals to an output terminal are made by turning on the desired pass transistor, where a "high" voltage to the control gate turns on a pass transistor and a "low" voltage to the control gate turns off a pass transistor. For example, if pass transistors 223, 225, and 232 are on (programmable cells 223A, 225A, and 232A apply "high" voltages), current flows through pass transistors 223, 225, and 232, thereby pulling voltages at output terminals 211-213 up to the voltages at input terminals 203, 201, and 204, respectively. The voltages at the input terminals can be from I/O pins, feedback from the GLBS, etc. The signals at output terminals 211-213 are then input to PAL 120 for ANDing.
As seen from FIG. 2, a GRP requires twelve programmable cells and pass transistors or switches in order to provide complete connectivity between the four input terminals and the three output terminals. However, as semiconductor technology continues to advance and functions become more complex, PLDs are needed to perform functions requiring larger numbers of inputs and input combinations, which necessitates larger sized routing devices. A typical PLD currently in use selects 16 out of 256 signals for transmission to a PAL for the ANDing function (e.g., a 2128 device from a 2K family of devices, such as from Lattice Semiconductor, Corp. of Hillsboro, Oreg.). Thus, in order to provide complete connectivity, 4,096 (16*256) programmable cells are required in the GRP.
However, implementation of a PLD having a GRP with over four thousand programmable cells and switches or interconnects is impractical. Thus, a GRP can be designed where the 256 input signals are partitioned into 16 groups of 16 signals. One signal is selected from each of the 16 groups and input into an AND array. Thus, 16 out of the 256 input signals are selected for ANDing. This reduces the number of programmable cells and interconnects from 4096 to 256 (16*16) for a 16-fold reduction. However, this reduction comes with the price of decreased connectivity because the 256 input signals can no longer be connected in any combination to 16 outputs.
FIG. 3 shows a 1.times.16 interconnection matrix 300 for selecting one of 16 signals. Sixteen matrices 300 allow 16 signals to be selected from 256 signals. Matrix 300 includes 16 pass transistors 301-316 coupled to 16 programmable cells 301A-316A, respectively, with each pass transistor coupled to a column signal line and all 16 pass transistors coupled to one row signal line, similar in operation to that of matrix 200 of FIG. 2. Matrix 300 has the 16 column signal lines coupled to 16 input terminals and the row signal line coupled to one output terminal. The output terminal is coupled to one input of a 16-input AND array 360. Thus, using this configuration, 16 of matrices 300, utilizing a total of 256 programmable cells, can be used to select 16 of 256 signals for transmission to the AND array. However, this configuration does not allow two or more signals from a group of 16 signals to be selected for inputting to the AND array. For example, if programmable cell 302A turns on pass transistor 302, thereby placing the signal at the associated input terminal 322 on the row signal line, the other 15 signals of the group at input terminals 321 and 323-336 cannot be selected.
FIG. 4 is another interconnection matrix 400 that allows greater selectivity of input signals by using two 1.times.32 matrices 400A and 400B coupled to the same group of 32 input signals. Matrices 400A and 400B each are a 1.times.32 matrix for selecting one of 32 input signals. Matrix 400A, which is the same as matrix 400B, includes 32 pass transistors 401-432 coupled to 32 programmable cells 401A-432A, respectively, with each pass transistor coupled to a column signal line and all 32 pass transistors coupled to one row signal line 497. Matrix 400 has the 32 column signal lines coupled to 32 input terminals 465-496 and the row signal line coupled to one output terminal. The output terminal is coupled to one input of a 16-input AND array 499. Eight pairs of matrices 400A and 400B allow 16 signals to be selected from 256 signals for input to AND array 499. Thus, instead of the interconnection matrix selecting one of 16 input signals from each of the 16 input signal groups, as with the matrix of FIG. 3, the matrix of FIG. 4 selects two of 32 input signals from each of 8 input signal groups, both resulting in the selection of 16 of 256 input signals.
However, with the matrix of FIG. 4, signal selectivity is increased. For example, if programmable cell 402A turns on pass transistor 402, thereby placing the signal at the associated input terminal (i.e., input terminal 466) on row signal line 497 for input to AND array 499, the other signals on the first group of 16 input terminals (i.e., input terminals 465 and 467-480) are not precluded from being selected as another input to the AND array. Thus, another one of the signals on input terminals 465 and 467-480 (and also on input terminals 481-496 representing the second group of 16 signals) can be selected as an input to AND array 499 by programming an associated programmable cell 433A and 435A-464A to turn on a corresponding one of pass transistors 433 and 435-464 for transmission via row signal line 498. Note that the signal on input terminal 466 can also be selected again for transmission via row signal line 498 by turning on programmable cell 434A.
Thus, by increasing the number of pass transistors and programmable cells from 16 to 32 for each of the 16 row signal lines, the selectivity of the GRP is increased. However, the increased selectivity requires doubling the number of programmable cells and pass transistors. Because, a GRP typically takes up 50% or more of the die area of a PLD, by increasing selectivity, the size of the GRP, and accordingly of the PLD, is greatly increased. In addition to an increase in size, the signal delay in transmission through the GRP increases with a larger number of transmission paths.
Accordingly, a routing or interconnect device is desired that overcomes the deficiencies described above of conventional routing devices.